1. Field of the Invention
This invention relates to solid state image sensors, and more specifically to active pixel image sensors.
2. Description of the Related Art
An active pixel sensor (APS) is an image sensor including an integrated circuit having an array of pixels, wherein each pixel typically contains a photodetector controlled by three or more transistors, or active circuitry elements. These active circuitry elements typically perform a pixel reset function, transfer charge, perform a voltage conversion, or are used in amplification. APS devices have been operated in a manner where each line or row of the imager is selected and then read out using a column select signal (analogous to a word and bit line in memory devices respectively). Conventionally, these components are provided for each photodetector and are located within a single pixel boundary.
FIG. 1A illustrates one pixel of a prior art image sensor. The pixel comprises a photodetector 10, a transfer gate 15, a floating diffusion region 20 for capacitive storage, a reset transistor 25, a row select transistor 40, and a source-follower transistor 45.
FIG. 1B schematically illustrates one pixel 100 of a prior art four transistor (4T) image sensor. The active elements of a pixel perform the functions of (1) photon to charge conversion by a photodiode 102; (2) transfer of charge to a floating diffusion node 108 by the transfer transistor 104; (3) resetting the floating diffusion node 108 to a known state before the transfer of charge to it by a reset transistor 106; (4) selection of a pixel cell or row of pixel cells for readout by a row select transistor 112; and (5) output and amplification of signals representing a reset-level voltage and a signal-level voltage based on the photo converted charges by a source-follower transistor 110, which has its gate connected to the floating diffusion node 108. The pixel 100 of FIG. 1B is formed on a semiconductor substrate as part of an imager device pixel array. The conventional four transistor (4T) pixel requires an operating voltage Vcc, as well as transfer gate (TG), row select (ROW) and reset (RST) control signals for operation.
FIG. 1C illustrates a block diagram of a CMOS imager device (“image sensor”) 120 having a pixel array 125, with each pixel cell being constructed as described above (see FIG. 1B), or as other known pixel cell circuits. The pixel array 125 comprises a plurality of pixels arranged in a number of columns and rows (not shown). The pixels of each row in the array 125 are all turned on by a row select line, and the pixels of each column are selectively output by respective column select lines. The row select lines are selectively activated in sequence by a row driver 130 in response to a row address decoder 135, and the column select lines are selectively activated in sequence for activation of each row by a column driver 140 in response to a column address decoder 145. Thus, a row and column address is provided for each pixel.
The CMOS imager is operated by a control circuit 150, which controls the address decoders 135 and 145 for selecting the appropriate row and column lines for pixel readout, and the row and column driver circuitry 130 and 140, which apply driving voltage to the drive transistors of the selected row and column lines. The pixel output signals typically include pixel reset signals Vrst, taken off of the floating diffusion nodes 108 when reset by reset transistors 106 and the pixel image signals Vsig, which are taken off the floating diffusion nodes 108 after photo-generated charges collected in the photodiode are transferred into the FD 108 by the transfer gate transistor 104. The Vrst and Vsig signals are read by a sample and hold circuit 155 and are subtracted by a differential amplifier 157, which produces a signal Vrst−Vsig for each pixel, which represents the amount of photons or light impinging on the pixels. These difference signals are digitized by an analog to digital converter 165. The digitized pixel signals are then fed to an image processor 170 to form a digital image. The digitizing and image processing can be located on or off the imager chip. In some arrangements, the differential signals Vrst−Vsig can be amplified as differential signals and directly digitized by a differential analog to digital converter.
A problem with prior art image sensors is that the inclusion of all these components within a single pixel results in a reduction in the fill factor of the pixel because it takes up area that could otherwise be used by the photodetector. This reduces the sensitivity, saturation signal and quantum efficiency of the sensor, which in turn adversely affects the performance parameters that are critical to obtaining good image quality. Additionally, inclusion of these active circuit elements within the pixel places a limitation on the minimum size of the pixel, which adversely affects the size and cost of the image sensor.
One approach to improving the fill factor and the sensitivity of an APS device is by reducing the amount of area allotted to components for each pixel while maintaining the desired features and functionality of the pixel architecture. Area reduction can be accomplished by sharing electrical components among multiple pixels. APSs in which electrical components are shared are said to have “shared architecture.”
Several schemes for sharing solid state components among pixels in an APS are disclosed, for example, in U.S. patent Publication No. 2006/0256221 A1 of McKee, published Nov. 16, 2006; U.S. patent application Ser. No. 11/207,744 of McKee et al., filed Aug. 22, 2005; U.S. patent application Ser. No. 11/213,937 of McKee et al., filed Aug. 30, 2005; and U.S. patent application Ser. No. 11/213,936 of McKee, filed Aug. 30, 2005 (collectively, “the McKee applications”). These disclosures include schemes for “2-way” sharing of electrical components between two pixels, and “4-way” sharing of electrical components among 4 pixels. For example, one or more of a floating diffusion region, source-follower amplifier, row select transistor, and reset transistor can be shared among multiple pixels to assist in increasing the fill factor of the pixel architecture.